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RedHawk-SC is the proven, trusted industry leader for power noise and reliability signoff for digital IP and SoCs down to 3nm and built on cloud-native elastic compute infrastructure.

Comprehensive IR Drop and Electromigration Signoff Solution for Digital IP and SoCs

Ansys RedHawk-SC is the industry’s trusted gold standard voltage drop and electromigration multiphysics sign-off solution for digital designs. Its powerful analytics quickly identify any weaknesses and allow what-if explorations to optimize power and performance. Redhawk-SC’s cloud-based architecture gives it the speed and capacity to handle full-chip analysis. Signoff accuracy is certified by all major foundries for all finFET nodes, down to 3nm.

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Ansys RedHawk-SC’s advanced power analytics (APA) deliver very high coverage for capturing dynamic power supply noise, thereby avoiding frequency loss due to unexpected dynamic voltage drop (DvD). It’s comprehensive DvD diagnostics quickly capture and measure the causes of dynamic IR-drop. A rich GUI and ‘what-if’ capability instantaneously report the voltage impact of design changes for IR ECO fixing. It analyzes thermal-aware current density in both signal and power net and provides statistical electomigration budgeting. Both vector and vectorless activity inputs are supported with advanced analytic capabilities that determine the timing impact of voltage variability (with Ansys Path FX™) as well as metrics that evaluate the robustness of power distribution networks.

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Chip-Package Co-Analysis Using Ansys RedHawk-CPA

How an integrated chip–package co-analysis can quickly and accurately model package layout for inclusion in on-chip power integrity simulations.


Ansys RedHawk-CPA is an integrated chip–package co-analysis solution that enables quick and accurate modeling of the package layout for inclusion in on-chip power integrity simulations using Ansys RedHawk. With RedHawk-CPA a designer can perform static IR drop analysis and AC hotspot analysis of the package layout following RedHawk static and dynamic analyses respectively. To ensure a reliable supply of power, and stable voltage levels at the transistor connection points, the entire system power delivery network (PDN) must be optimized and validated, including the impact of package on a chip.

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IR Drop Analysis in Physical Design | IR Analysis in VLSI

In this article, we will discuss what is ir drop in asic design, why ir drop issue occurs, what are the effects of ir drop and how to analyze and prevent the ir drop issue., what is ir drop issue:, the power supply (vdd and vss) in a chip is uniformly distributed through the metal rails and stripes which is called power delivery network (pdn) or power grid. each metal layers used in pdn has finite resistivity. when current flow through the power delivery network, a part of the applied voltage will be dropped in pdn as per the ohm’s law. the amount of voltage drop will be v = i.r, which is called the ir drop. figure-1 shows the ir drop in the power net. any metal net can be assumed as a combination of small r and c. , if the resistivity of metal wire is high or the amount of current following through the power net is high, a significant amount of voltage may be dropped in the power delivery network which will cause a lesser amount of voltage available to the standard cells than the actual amount of voltage applied. , standard cells or macros sometimes do not get the minimum operating voltage which is required to operate them due to ir drop in power delivery network even the application of sufficient voltage in the power port. voltage drop in the power delivery network before reaching the standard cells is called ir drop., this drop may cause the poor performance of the chip due to the increase of delay of standard cells and may cause the functional failure of the chip due to setup/hold timing violation. to avoid this issue, ir analysis must be done and consider its effect in timing analysis in the design cycle. , types of ir drop:, there are two types of ir drop in the asic design:, static ir drop, dynamic ir drop, static ir drop is the voltage drop in the power delivery network (pdn) when there are no inputs switching means the circuit is in the static stage. whereas dynamic ir drop is the voltage drop in the power delivery network when the inputs are continuously switching means the circuit is in a functional state. dynamic ir drop will depend on the switching rate of instance., when the inputs are switching continuously, more current would flow in the instances and also in pdn. so there will be more ir drop in the pdn. therefore dynamic ir drop is more than the static ir drop., reasons for ir drop:.

Effects of IR drop:

IR analysis and fixes:

Every eda companies have their own ir analysis tool which performs the ir analysis and based on the analysis the techniques for the ir fixes are applied. two most popular tools for ir analysis used in industry are:, redhawk of ansys voltus of cadence design system, based on the analysis there are various techniques to fix the ir drop are applied. some of the fixes which generally performed are:, insertion of the sufficient number of de-cap cells which will boost the power delivery network.  reconstruct the power delivery network if it is not built properly. we could increase the width of the metal stripes or could decrease the separations between them we could spread the logic cells in a region so that the load can be distributed, thanks you, leave a comment cancel reply.

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An efficient approach to evaluate Dynamic and Static voltage-drop on a multi-million transistor SoC design

Set-Top-Box SoC wire-bond and its adaptation for a flipchip : testcase and results

By Abhishek Nigam, Vivek Sinha (ST Microelectronics)

As Set-Top-Box(STB) SoC designs become extremely complex with multi-million gates, lowering of voltage supplies, and multiple clock domains including high and low frequencies, evaluating the power-integrity of a chip has become one of the key challenges in design and ensuring good yield.

This paper describes the methodology and technology we used, to assess full-chip dynamic and static IR-drop for such complex and huge SoCs. Firstly, it outlines power-grid weakness and hot spot exploration using a testcase of STB SoC in 65nm WireBond and Flipchip variants. Additionally, it outlines the complexity in performing voltage drop analysis in vector-less mode without a VCD in terms of methodology and technology, specifically due to flipchip complexity.

Finally, the paper describes the key implementation approaches using Ansys’ RedHawk tool and power-trends observed on such SoCs. Using this approach SoC designers will be in a position to analyze dynamic voltage waveforms for every place-able instance on a power-grid, early in the design process, explore “hot spots”, as well as verify full-chip power-integrity in the design flow - a value-ad to SoC implementation flows.


1. Set-Top-Box SoC designs are complex, typically with over 100 million transistors, having multiple frequencies and low voltage supply of 1.1V in 65 nm technology node. In the past, others have tried to evaluate P/G weakness, computed the resistance of each cell from its P/G pins to the power pads, and then generated a report identifying high resistance paths, static voltage drop analysis and hot-spot exploration on SoC with Wirebond package. Most of the times undetected Silicon IR drop may lead to appropriate voltage not reaching a transistor, which can to an extent be compensated by increasing the supply at board level. In extreme cases, it could also lead to customer-returns, because of a Timing Analysis failure, whose root-cause could be eventually found to be due to higher-than-rated, voltage drop on operation. Dynamic Voltage drop is something that cannot be modeled by pure traditional Static Timing Analysis. So, the need to calculate and model the dynamic IR drop on SoCs was a driver for formulation and execution of the idea as explained in this paper. A specific problem was the non-feasibility of creating a Value Change Dump (VCD) file for “functional mode” for such an extremely large SoC which may contain actual switching information. Ansys Redhawk tool provided a dynamic simulator which uses an internal statistical approach towards vector-less dynamic IR drop analysis but which covers realistic worst case switching scenarii. This methodology was exploited on STB variants (wire-bond and flipchips), as summarized in Figure 11, to assess their Dynamic IR drop and compare with corresponding Static results. This approach can be re-used on similar large SoCs to evaluate their Dynamic voltage drop behaviours, and better prepared before Si-out.

2. Scope of STB SOC WireBond(WB) and FlipChip(FC) analysis:

While calculating dynamic voltage drop on STB Flip chip variants, the added complexity was that they were created keeping location of IO-pads at the die-edge which is the classical position as in Wirebond pad-limited SoCs. It means, power supply eventually arrives to the core, from the die-edge. This methodology was done specific to both STB Flip chip PG tapes, as we were constrained by mask-layer compatibility to previous wire bond chip. We had to ensure base-layer compatibility up to Metal-6, which is why we were obliged to preserve the classical IO pads at the periphery, even though there existed central power bumps. In other words, the routing from central power bumps up to the pad-openings is also contributing to IR drop, in this case.

1. The STB design statics and power summary representation in Figure 1:

Power summary in Figure 1 is Cell Type based, Frequency based and power components based. Switching scenario is derived statically and depends on several design-aware factors such as:

We have supplied known core power data of 1.2Watts, Redhawk performs scaling of the toggle rate for the block, instance or cell to achieve more accurate analysis for instances. Dominant operating frequency on the chip is defined as 100MHz, the lowest frequency that includes 96% of the power consumption on the chip. STA file from Primetime was generated in Functional mode Worst

case corner. SPEF files are generated through Synopsys RC extractor.

2. Design Weakness in STB Wire-bond and Flip-chip variants

Design Weakness is similar as only RDL/package has changed and not Place and Route database.

In Static voltage drop, Instance will draw the current all the time, it does not matter when the instance switches. In Dynamic voltage drop, Instances will draw transient current only when it switches. Non-switching instance will draw only leakage current. Dynamic analysis will see the real peak demand current on the chip.

3. Static Voltage drop in STB Wire-bond and Flip-chip variants.

4. Voltage drop analysis in STB WireBond

4.1 Dynamic Voltage drop map and Hot Spot exploration.

5. Voltage drop analysis in Set-Top-Box SOC FC_2RDL (RDL1 – Alucap , RDL2-Cu)

Certain data, such as redistribution layer (RDL) in Figure 4 and flip-chip bump layer descriptions, are available in GDSII format. This type of data must be converted to DEF/LEF format for integration into Redhawk database. gds2def utility was key, can output smooth 45-degree geometries in DEF for power/ground routing, including IO rings and RDL. Flowchart in Figure 5 depicts adaptability and flexibility in ignoring AP layer only in available top and partition DEF’s design constraint of redhawk for Set-Top-Box SOC Flip-chip in which AP layer was used as first RDL.

Redistribution Layer in Alucap(AP) can be seen for which need to be extracted for Core Voltage drop.

Figure 6 ( Redhawk flow )

5.1 Dynamic Voltage drop map and Hot Spot exploration.

Note : In Figure 3 big difference in demand current and battery current indicates the effectiveness of decaps.Dynamic simulation time, 10000 psec, to include 96.8977% of power consumption on the chip.

6. Voltage drop analysis in Set-Top-Box SOC FC_8ML (RDL1-M8,RDL2-AP)

In this methodology the two redistribution layers used were M8 and AP. M8 layer was used instead of the “external Cu” as compared to the previously described flipchip variant. The Redhawk flow remains the same as shown in Figure 5.

5.2 Dynamic Voltage drop map and Hot Spot exploration.

7. Conclusion:

Flow and methodology used by Redhawk tool helped in evaluating Dynamic Voltage drop without a dependency on a VCD for Set-Top-Box SOC , wirebond and flipchip variants. This added value over traditional Static IR drop methods and their limitations. Also, this exercise provided a perspective to the Digtial Convergence Group (DCG) validation team, to understand one of the reasons for the real need to increase supply voltage on Set-Top-Box SOC FC_2RDL Silicon.

SoC Power-trends (Figure 11) of Static versus Dynamic Voltage drop on Wirebond and Flip-chip packages, was demonstrated on representative test-cases. Finally, this approach led to development of a specific CAD method, which has potential for re-use. Limitations are, not having used parasitics netlist for L(di/dt) drop modeling of package and die inductances, and the absence of Apache Power Library(APL) for this 65nm technology node.

Power-figures as observed on Set-Top-Box SOC WB, FC_2RDL and FC_8ML

8. Acknowledgements

9.1 Appendix -1 : Die-photo.

Note: Set-Top-Box SOC FC_2RDL SoC and DDR memory fabricated on the same package!

9.2 Appendix -2 Redhawk Tool flow and Gate-level Power Calculation method

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IR Drop Analysis


What is IR Drop Analysis? How it effects the timing?

The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current start flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. This Drop is called as IR Drop.

For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this context can allow upto 0.4 volts drop which does not effect the timing and functionality of design.

Liittyvät Viestit

Floorplanning, static timing analysis (sta) overview, physical design flow, how it effects the timing.

IR Drop is Signal Integrity(SI) effect caused by wire resistance and current drawn off from Power (Vdd) and Ground (Vss) grids. According to Ohms law, V = IR. If wire resistance is too high or the current passing through the metal layers is larger than the predicted, an unacceptable Voltage drop may occur. Due to this un acceptable voltage drop, The power supply voltage decreases. That means the required power across the design is not reaching to the cells. This results in increased noise susceptibility and poor performance.

The design may have different types of gates with different voltage levels. As the voltage at gates decreased due to unacceptable voltage drop in the supply voltage, the gate delays are increased non-linearly. This may lead to setup time and hold time violations depending on which path these gates are residing in the design.

As technology node shrinking, there is decrease in the geometries of the metal layers and the resistance of this wires increased which lead to decrease in power supply voltage. During Clock Tree Synthesis, the buffers and inverters are added along the clock path to balance the skew. The voltage drop on the buffers and inverters of clock path will cause the delay in arrival of clock signal, resulting hold violation.

What are the tools used for IR Drop Analysis? In which stage IR Drop Analysis performed ?

Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache are mainly used to show IR Drop on chip. Here we are going to discuss about IR Drop using Redhawk. IR Drop Analysis using Redhawk is possible at different stages of the design flow.

When changes are in expensive and they don’t effect project’s schedule, It is better to use Redhawk for IR drop analysis from start of the design cycle. It can identify and fix power grid problems in the design. This also reduces changes required in sign-off stage where final static and dynamic voltage (IR) drops performed.

So Redhawk can be used anywhere in the design starting from the floorplanning stage through initial and final cell placement stages.

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Full Chip IR Drop Analysis using Distributed Multi Processing

IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared to silicon behavior. Apache has been providing IR drop analysis tools for about a decade now, and Aveek Sarkar spoke with me this afternoon about how they have used Distributed Multi Processing (DMP) to scale up the analysis.

Q: When did you start at Apache?

I’ve been at Apache for 10 years now, and am employee #12.

Q: What are the challenges of IR drop analysis?

One challenge is how to compute the actual Idd and Iss currents from board to package to chip, because these values are time-dependent.

Global IR drop analysis is required, it cannot be divided into smaller blocks. Other types of analysis can be divided into smaller pieces that are then sent to different CPUs.

The IR drop challenge is not solved by divide and conquer in our approach.

Consider an SoC with an ARM CPU plus a GPU, these IPs can have different VDD nets but can end up sharing the VSS net – so they are connected electrically, and therefore cannot be partitioned for IR drop analysis.

The effect of package and board must be taken into account with the IC, so all three levels must be simulated together.

Q: How is your approach different for IR drop analysis?

We partition our anlaysis while keeping the global effects intact, so we call our approach DMP – this uses a cluster of machines. We see very similar results on a clustered approach as compared to a single CPU when run flat. There is less than a 3% difference, while the DMP capacity is 3X bigger, and run time is 2X faster (versus full-flat analysis).

We’re using smart-partitioning, where the integrated effect is taken into account. The Redhawk tool user just uses the Cluster on their design. At the end of analysis you get to visualize the results in the GUI, seeing the entire results and the result looks just like a flat analysis.

Q: How do I know the proper size cluster to use?

RedHawk has an explorer feature which will recommend the machine requirements. Our factory also consults with ASIC customers to recommend the best cluster.

Q: How do i know if Redhawk results are accurate?

You can build and measure silicon to convince yourself of the accuracy. Companies like AMD have presented at DAC this year where silicon results were provided, with good correlation to simulated.

Q: What is the status of Redhawk using DMP technology?

DMP is in early use as Beta right now, our 2nd level of customers will be added by December, and by DAC next year we will be in production release.

We typically have two product releases per year.

Q: How similar is IR drop analysis to SPICE circuit simulation with transient analysis?

They are very similar electrical ideas in terms of current and voltage calculations. We linearize the problem and make it a scalable problem using DMP. We could have 1+ billion nodes to solve, and we do it efficiently. We do a very accurate time-domain analysis going down to time-step of say 5ps or so.

Q: How much analysis speedup should I expect with my cluster of CPUs?

The analysis speedup is sublinear, so going from 4 to 16 CPUs will show less than 4X speed improvement given the nature of the problem we solve.

Q: How do I start an evaluation of Redhawk using DMP?

For an evaluation contact me at the factory.

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Ansys Redhawk training is a 5 weeks training program focused on standard power noise and reliability sign-off solution for SOC designs.

ir drop analysis using redhawk

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Ansys Redhawk training is a 5 weeks training program focused on standard power noise and reliability sign-off solution for SOC designs. Redhawk helps create high-performance SoCs which are power efficient and reliable for electro migration, thermal and electrostatic discharge issues. Redhawk is the sign-off solution for all the foundries. Redhawk’s advanced Distributed Machine Processing (DMP) enables significantly higher capacity and better performance for full-chip IR/dynamic voltage drop, power/signal electro migration (EM) and electrostatic discharge (ESD) analyses.

Redhawk training focuses on all the aspects Power integrity, and IR drop analysis.

Power Integrity and IR Drop Analysis Theory

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Fast dynamic ir-drop prediction using machine learning in bulk finfet technologies.

ir drop analysis using redhawk

1. Introduction

2. proposed technique, 2.1. proposed flow, 2.2. nature feature extraction, 2.3. neighboring feature construction, 2.4. design matrix construction, 2.5. training model, 3. experiments setup, 4.1. ir-drop prediction before eco, 4.2. ir-drop prediction after eco, 4.3. runtime comparison, 5. conclusions, author contributions, institutional review board statement, informed consent statement, data availability statement, conflicts of interest.

Share and Cite

Huang, P.; Ma, C.; Wu, Z. Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies. Symmetry 2021 , 13 , 1807. https://doi.org/10.3390/sym13101807

Huang P, Ma C, Wu Z. Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies. Symmetry . 2021; 13(10):1807. https://doi.org/10.3390/sym13101807

Huang, Pengcheng, Chiyuan Ma, and Zhenyu Wu. 2021. "Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies" Symmetry 13, no. 10: 1807. https://doi.org/10.3390/sym13101807

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How to perform IR drop analysis of Analog IP using Redhawk/Totem

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