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system verilog conditional assignment

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Generate Conditional Assignment Statements in Verilog

I'm trying to create a simple crossbar style interconnect between N masters and M slaves.

Say if I have 2 Masters and 2 Slaves, the crossbar connects them as follows:

Is there a way to generate the above assign statements if number of master and slaves are parameters? Or is there any other way to accomplish what I'm trying to do? Any help would be appreciated.

Greg's user avatar

2 Answers 2

You can use generate blocks in this case:

What I illustrated here are only the assigns for addr . You'd had to have data and any other master to slave signals to this loop and create another loop where you loop over masters first and then slaves to assign resp and any other slave to master signals.

I've used an intermediate wire for addr to be able to have an assign statement per master. This way, when a master is granted it will drive the wire, otherwise it will drive high impedance. It's therefore vital to not grant two or more masters at the same time.

It isn't exactly what you have, but you can replace the multiple assigns with a priority encoding scheme if you want to allow multiple masters at the same time.

Tudor Timi's user avatar

The muxing logic can be scaled withing a combinational block. The example below defaults in assignments to zero then updates the assignments with LSB priority.

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An introduction to SystemVerilog Operators

In this post, we talk about the different operators which we can use in SystemVerilog. These operators provide us with a way to process the digital data in our verilog designs.

This processing can be extremely simple, as is the case with simple logic gates . However, we may also need to perform complex logical or mathematical operations on our data.

In any case, SystemVerilog provides us with a number of operators which allow us to perform a wide range of different calculations or operations on our data.

In most instances when we use SystemVerilog operators, we create boolean expressions or logic circuits which we want to synthesize . However, there are also some operators which we can't use to write synthesizable code.

The SystemVerilog operators are entirely inherited from verilog. Therefore, if you are already familiar with verilog it is not necessary to read this post.

Let's take a closer look at the various different types of operator which we can use in our SystemVerilog code.

SystemVerilog Bit Wise Operators

We use the bit wise operators to combine a number of single bit inputs into a single bit output. In addition.

We most commonly use the bit wise operators to model logic gates in SystemVerilog.

The table below shows the full list of bit wise operators which we can use in SystemVerilog.

The SystemVerilog code below shows how we use each of these operators in practise.

We have seen in the previous section how we can use the bitwise operators to combine 2 or more single bit inputs.

However, we can also use the bit wise operators on SystemVerilog vector types to reduce them to a single bit.

When we do this, we pass only the name of the vector that we want to reduce preceded by the operator.

All of the bits in the vector are then reduced to a single bit by applying the relevant logical operation to them.

For example, if we had a 2 bit vector and applied the and reduction operation , the result would be an and of the 2 bits in the vector.

When we use the bit wise operators in this way, they are commonly referred to as reduction operators .

The code snippet below shows how we use the reduction operators in practice. We can also simulate these examples on EDA playground.

As we can see from this, we can use all of the bit wise operators except for the not operator to perform vector reductions.

We use arithmetic operators to perform basic mathematic functions on our variables. These operators should already be familiar as they are mostly replications of common mathematic symbols.

However, these operators also require some consideration when we use them with synthesizable code.

The plus, minus and multiplication operators can all be synthesised by most modern tools.

However, this can often result in sub-optimal logical performance. As a result, it can be necessary to design logic circuits which specifically perform these functions.

Alternatively, we may wish to use DSP blocks within our FPGA to perform these operations more efficiently.

We should never use the modulus, exponential or divide operators for synthesizable code as most tools will be unable to handle them.

The table below shows the full list of arithmetic operators in SystemVerilog.

The code snippet below shows how we use each of these operators in practise.

We use relational operators to compare the value of two different variables in SystemVerilog. The result of this comparison returns either a logical 1 or 0 , representing true and false respectively.

These operators are similar to what we would see in other programming languages such as C or Java .

In addition to this, most of these operators are also commonly used in basic mathematics expressions so they should already feel familiar.

The table below shows the full list of relational operators in SystemVerilog.

The SystemVerilog code below shows how we use each of the relational operators in practise.

The SystemVerilog logical operators are similar to the bit-wise operators we have already seen.

However, rather than using these operators to model gates we use them to combine relational operators. As a result, we can build more complex expressions which can perform more than one comparison.

As with relational operators, these expressions return either a 1 (true) or 0 (false).

There are only three logical operators which we can use in SystemVerilog. Again, these are similar to operators which are used in languages such as C or Java.

The table below shows the full list of logical operators in SystemVerilog.

The SystemVerilog code below shows how we use each of the logical operators in practise.

Again, it is important that we use parentheses to separate the different elements in our expressions when using these operators.

In addition to the operators we have already seen, there are a few extra operators which we can use for specific logical functions.

One of the most useful and commonly used of these special functions are the shift operators, which are shown in the table below.

When designing digital circuits, we frequently make use of shift operations . As a result, SystemVerilog provides us with a simple technique for implementing these functions.

The shift operator actually requires two arguments. The first of these is the name of the signal which we want to shift. The second argument is the number of bits we want to shift.

When we use the logical shift operators, all the blank positions are filled with 0b after the signal has been shifted by the required number of bits.

In contrast, the arithmetic shift operators preserve the sign of the shifted signal. As a result of this, they should only be used with signed data types.

The code snippet below shows how we use the shift operators in practise.

In SystemVerilog, we use a construct known as the conditional operator to assign data to a signal based on a conditional statement .

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

This operator may already be familiar as it is also used in other programming languages such as C and Java . However, in this case it is known as the ternary operator.

The code snippet below shows the general syntax for the SystemVerilog conditional operator.

When the expression given in the <condition> field evaluates as true, then the output is set to the value given in the <true> field.

If the conditional expression evaluates as false, then the output is set to the value given by the <false> field.

The code snippet below shows a practical example of the SystemVerilog conditional operator. In the a future post in this series, we see how we can use the conditional operator model multiplexors.

The final types of SystemVerilog operator which we can use are the concatenation and replication operators.

In both instances, the output of these operators are a vector type. However, the inputs to both of these operators can be either single bit or vector types.

Both of these SystemVerilog operators are shown in the table below.

We use the SystemVerilog concatenation operator to combine two or more signals into a vector.

As an example, we may have 2 single bit signals which we want to combine to use as an address for a multiplexor.

To use the concatenation operator, we list the signals which we wish to combine within the curly brackets. We separate this list of signals using a comma.

When we use the SystemVerilog concatenation operator, the bits in the output match the order in which they are listed inside the brackets.

For example, the code snippet below would result in a output vector which has the value 0011b.

We use the replication operator to assign the same value to a number of bits in a vector.

For example, if we wanted to assign all of the bits of a vector to 0b then we would use the replication operator.

When we use the replication operator we have to specify both the signal or value we want to replicate and the number of times we want to replicate it.

The SystemVerilog code below show how we use the concatenation and replication operators in practice.

Which type of operators do we use to model logic gates in SystemVerilog?

We use the bit wise operators to model logic gates in verilog.

Two of the arithmetic operators should not be used with synthesizable code – name them.

The division and modulus operators can’t be synthesized.

What is the difference between the bit wise and logical operators?

The bit wise operators work on individual bits whereas the logical operators are used to combine logical expressions.

What is the difference between the logical shift operators and the arithmetic shift operators.

The logical shift operators pad the blank positions with 0b whereas the arithmetic operator preserves the sign of the signal.

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Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

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IMAGES

  1. 😍 Verilog assignment. Conditional Operator. 2019-02-03

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  2. 😍 Verilog assignment. Conditional Operator. 2019-02-03

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  3. System Verilog Tutorial

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  4. 😍 Verilog assignment. Conditional Operator. 2019-02-03

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  5. 😍 Verilog assignment. Conditional Operator. 2019-02-03

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  6. Verilog ‘if-else’ vs ‘case’ statements

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COMMENTS

  1. Conditional Assignment in Verilog

    You have a compound conditional assignment. There are 3 conditions: the expressions within parentheses. You understand how the 1st condition works. That's great. The 2nd condition works in a similar fashion: if the condition is true, then assign out to out_2. In this case, the condition is a constant, not a variable.

  2. If Statements and Case Statements in SystemVerilog

    SystemVerilog If Statement The if statement is a conditional statement which uses boolean conditions to determine which blocks of SystemVerilog code to execute. Whenever a condition evaluates as true, the code branch associated with that condition is executed. This statement is similar to if statements used in other programming languages such as C.

  3. Generate Conditional Assignment Statements in Verilog

    Generate Conditional Assignment Statements in Verilog Ask Question Asked 8 years, 3 months ago Modified 8 years, 3 months ago Viewed 4k times 1 I'm trying to create a simple crossbar style interconnect between N masters and M slaves. Say if I have 2 Masters and 2 Slaves, the crossbar connects them as follows:

  4. Conditional Operator

    It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used: condition ? value_if_true : value_if_false Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”.